SRBR_STHR0 (SRBR_STHR0) – Offset 30
NOTE: There are a total of 16 Shadow Receive Buffer Registers (SRBR_STHR[15:0]. The register description is the same for all of them. The other registers are at the following offsets:
SRBR_STHR1 at offset 34h
SRBR_STHR2 at offset 38h
SRBR_STHR3 at offset 3Ch
..........
SRBR_STHR14 at offset 68h
SRBR_STHR15 at offset 6Ch
Bit Range | Default | Access | Field Name and Description |
30:8 | - | - | Reserved |
7:0 | 0h | RW | srbr_sthr0 (srbr_sthr0) Used as SRBR: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. Used as STHR: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as toaccommodate burst accesses from the master. This register contains data to be transmitted on theserial output port (sout) in UART mode. Data should only be written to the THR when the THR Empty(THRE) bit (LSR[5]) is set. If FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THRclears the THRE. Any additional writes to the THR before the THRE is set again causes the THR datato be overwritten. If FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may bewritten to the THR before the FIFO is full. The number x (default=16) is determined by the value ofFIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full resultsin the write data being lost. |