Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Capabilities (capabilities) – Offset 40
This register provides the host driver with information specific to the host controllerimplementation. Please note, that the default values shown here assume no bypass of thecapabilities register. In case software decides to bypass the default capabilities register valuesthe reset values will present the bypassed value.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
62:35 | - | - | Reserved
|
34 | 1h | RO | DDR50 Support (corecfg_ddr50support) This bit indicates whether DDR50 is supported. |
33 | 1h | RO | SDR104 Support (corecfg_sdr104support) This bit indicates whether SDR104 is supported.SDR104requires tuning. |
32 | 1h | RO | SDR50 Support (corecfg_sdr50support) This bit indicates whether SDR50 is supported. |
31:30 | 1h | RO | Slot Type (corecfg_slottype) This field indicates usage of a slot by a specific HostSystem. (A host controller register set is defined perslot.) Embedded slot for one device (01b) means thatonly one on-removable device is connected to a SD busslot. Shared Bus Slot (10b) can be set if Host Controllersupports Shared Bus Control register.The Standard Host Driver controls only a removablecard or one embedded device is connected to a SD busslot. |
29 | 0h | RO | Asynchronous Interrupt Support (corecfg_asynchintrsupport) This bit indicates whether the HC supportsAsynchronous Interrupt |
28:27 | - | - | Reserved
|
26 | 1h | RO | Voltage Support 1.8V (corecfg_1p8voltsupport) This bit indicates whether the HC supports 1.8V. |
25 | 0h | RO | Voltage Support 3.0V (corecfg_3p0voltsupport) This bit indicates whether the HC supports 3.0V. |
24 | 0h | RO | Voltage Support 3.3V (corecfg_3p3voltsupport) This bit indicates whether the HC supports 3.3V. |
23 | - | - | Reserved
|
22 | 1h | RO | SDMA Support (corecfg_sdmasupport) This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. (SDMA Mode) |
21 | 1h | RO | High Speed Support (corecfg_highspeedsupport) This bit indicates whether the HC and the Host System support High Speed mode. |
20:18 | - | - | Reserved
|
17:16 | 2h | RO | Max Block Length (corecfg_maxblklength) This value indicates the maximum block size that the HDcan read and write to the buffer in the HC.The buffer shall transfer this block size without waitcycles. Sizes can be defined as indicated below. |
15:8 | C8h | RO | Base Clock Frequency for SD Clock (corecfg_baseclkfreq) (1) 6-bit Base Clock Frequency This mode is supportedby the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0.Unit values are1MHz. The supported clock rangeis 10MHz to 63MHz. |
7 | 1h | RO | Timeout Clock Unit (corecfg_timeoutclkunit) This bit shows the unit of base clock frequency used todetect Data Timeout Error. |
6 | - | - | Reserved
|
5:0 | 01h | RO | Timeout Clock Frequency (corecfg_timeoutclkfreq) This bit shows the base clock frequency used to detectData Timeout Error. |