Status (STS) – Offset 6 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
- DEVIDLE Control (HECI1_DEVIDLEC)
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
- Function Configuration (FNCFG)
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
- Power Management Control (PMCTL)
Keyboard and Text (KT) Additional Configuration
- Power Management Control and Status (KT_CSXE_PMD_PMCSRBSE_PMCSR)
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
SATA MXTBA
SDXC (SD Card) PCR
- Dynamic Clock Gating Control (GPPRVRW1)
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

Status (STS) – Offset 6

Status.

Bit Range	Default	Access	Field Name and Description
15	0b	RW/1C	Detected Parity Error (DPE) Set when the bridge detects a parity error on the internal backbone. This bit gets set even if CMD.PERE is not set.
14	0b	RW/1C	Signaled System Error (SSE) Set when the LPC bridge signals a system error to the internal SERR# logic.
13	0b	RO	Received Master Abort (RMA) Set when the bridge receives a completion with unsupported request status from the backbone. LPC is a target only controller.
12	0b	RO	Received Target Abort (RTA) Set when the bridge receives a completion with completer abort status from the backbone. LPC is a target only controller.
11	0b	RW/1C	Signalled Target Abort (STA) Set when the bridge generates a completion packet with target abort status on the backbone.
10:9	01b	RO	DEVSEL# Timing Status (DTS) Indicates medium timing, although this has no meaning on the backbone.
8	0b	RW/1C	Data Parity Error Detected (DPD) Set when the bridge receives a completion packet from the backbone from a previous request, and detects a parity error, and CMD.PERE is set.
7	0b	RO	Fast Back to Back Capable (FBC) Reserved.
6	-	-	Reserved
5	0b	RO	66 MHz Capable (C66) Reserved.
4	0b	RO	Capabilities List (CLIST) There is a capabilities list in the LPC bridge.
3:0	-	-	Reserved

Revision ID (RID)

Device Command (CMD) Revision ID (RID)