Host Control 1 (hostcontrol1) – Offset 28 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Host Control 1 (hostcontrol1) – Offset 28

Bit Range	Default	Access	Field Name and Description
7	0h	RW	Card Detect Signal Detection (hostctrl1_cdsigselect) This bit selects source for card detection. 1- The card detect test level is selected 0 -SDCD# is selected (for normal use)
6	0h	RW	Card Detect Test Level (hostctrl1_cdtestlevel) This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal int sts enable bit is set. 1 - Card Inserted 0 - No Card
5	0h	RW	Extended Data Transfer Width (hostctrl1_extdatawidth) This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controlled by Data Transfer Width in the Host Control 1 register. This bit is not effective when multiple devices are installed on a bus slot (Slot Type is set to 10b in the Capabilities register). In this case, each device bus width is controlled by Bus Width Preset field in the Shared Bus register. 1 - 8-bit Bus Width 0 - Bus Width is Selected by Data Transfer Width
4:3	0h	RW	DMA Select (hostctrl1_dmaselect) One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. 00 - SDMA is selected 01 - 32-bit Address ADMA1 is selected 10 - 32-bit Address ADMA2 is selected 11 - 64-bit Address ADMA2 is selected.
2	0h	RW	High Speed Enable (hostctrl1_highspeedena) This bit is optional. Before setting this bit, the HD shall check the High Speed Support in the capabilities register. If this bit is set to 0 (default), the HC outputsCMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/ 20MHz for MMC). If this bit is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52MHz for MMC)/ 208Mhz (for SD3.0)If Preset Value Enable in the Host Control 2 register is set to 1, Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitches. After setting this field, the Host Driver sets SD Clock Enable again 1 - High Speed Mode 0 - Normal Speed Mode
1	0h	RW	Data Transfer Width (hostctrl1_datawidth) This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. 1 - 4 bit mode 0 - 1 bit mode
0	0h	RW	LED Control (hostctrl1_ledcontrol) This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction. 1 - LED on 0 - LED off