Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
PCI Command & Status Register (PCICMD_STS) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0x0 | RW/V | Detected Parity Error (DPE) 0 = No parity error detected. |
30 | 0x0 | RW/V | Signaled System Error (SSE) 0 = No system error signaled. |
29 | 0x0 | RW/V | Received Master Abort (RMA) 0 = Root port has not received a completion with unsupported request status from the backbone. |
28 | 0x0 | RW/V | Received Target Abort (RTA) 0 = Root port has not received a completion with completer abort from the backbone. |
27 | 0x0 | RW/V | Signaled Target Abort (STA) 0 = No target abort received. |
26:25 | 0x0 | RW/V | DEVSEL# Timing Status (DEV_STS) Hardwired to 0. |
24 | 0x0 | RW/V | Master Data Parity Error Detected (DPED) 0 = No data parity error received. |
23 | 0x0 | RW/V | Fast Back to Back Capable (FB2BC) Hardwired to 0. |
22 | - | - | Reserved
|
21 | 0x0 | RW/V | 66 MHz Capable () Hardwired to 0. |
20 | 0x1 | RW/V | Capabilities List () Hardwired to 1. Indicates the presence of a capabilities list. |
19 | 0x0 | RW/V | Interrupt Status () Indicates status of hot-plug and power management interrupts on the rootport that result in INTx# message generation. |
18:11 | - | - | Reserved
|
10 | 0x0 | RW | Interrupt Disable (INT_DIS) This disables pin-based INTx# interrupts on enabled hot-plug and powermanagement events. This bit has no effect on MSI operation. |
9 | 0x0 | RW/V | Fast Back to Back Enable (FBE) Hardwired to 0. |
8 | 0x0 | RW | SERR# Enable (SEE) 0 = Disable |
7 | 0x0 | RW/V | Wait Cycle Control (WCC) Hardwired to 0. |
6 | 0x0 | RW | Parity Error Response (PER) 0 = Disable. |
5 | 0x0 | RW/V | Palette Snoop Enable (PSE) Hardwired to 0. |
4 | 0x0 | RW/V | Postable Memory Write Enable (PMWE) Hardwired to 0. |
3 | 0x0 | RW/V | Special Cycle Enable (SCE) Hardwired to 0. |
2 | 0x0 | RW | Bus Master Enable (BME) 0 = Disable. All cycles from the device are master aborted |
1 | 0x0 | RW | Memory Space Enable (MSE) 0 = Disable. Memory cycles within the range specified by the memory base and limit registers aremaster aborted on the backbone. |
0 | 0x0 | RW/V | I/O Space Enable (IOSE) This bit controls access to the I/O space registers. |