Power Management 1 Control (PM1_CNT) – Offset 4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
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CNVi PCI Configuration
DCI PCR
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xHCI Configuration
xHCI Memory Mapped

Power Management 1 Control (PM1_CNT) – Offset 4

Lockable: No

Usage: ACPI or Legacy

Power Well: Bits 0-9, 13-31: Primary, Bits 10-12: RTC

Bit Range	Default	Access	Field Name and Description
30:14	-	-	Reserved
13	0b	WO	Sleep Enable (SLP_EN) This is a write-only bit and reads to it always return a zero. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. This bit is reset by PLTRST# assertion.
12:10	000b	RW	Sleep Type (SLP_TYP) This 3-bit field defines the type of Sleep the system should enter when the SLP_EN bit is set to 1. Bits Mode Typical Mapping 000 ON S0 001 Reserved 010 Reserved 011 Reserved 100 Reserved 101 Suspend-To-RAM S3 110 Suspend-To-Disk S4 111 Soft Off S5 These bits are reset by RTCRST# only.
9:3	-	-	Reserved
2	0b	WO	Global Release (GBL_RLS) This bit always reads as 0. ACPI software writes a '1' to this bit to raise an event to the BIOS. BIOS sfotware has corresponding enable and status bits to control its ability to receive ACPI events.
1	-	-	Reserved
0	0b	RW	SCI Enable (SCI_EN) Selects the SCI interrupt or the SMI# for various events. 0 = These events will generate an SMI#. 1 = These events will generate an SCI. This bit is reset by PLTRST# assertion.

Power Management 1 Timer (PM1_TMR)

Power Management 1 Enables and Status (PM1_EN_STS) Power Management 1 Timer (PM1_TMR)