Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Input/Output Stream Descriptor x Cyclic Buffer Length (ISD0CBL) – Offset 88
NOTE: This register applies to the following input and output streams at the corresponding offsets:
Input stream 0: offset 88h
Input stream 1: offset A8h
Input stream 2: offset C8h
Input stream 3: offset E8h
Input stream 4: offset 108h
Input stream 5: offset 128h
Input stream 6: offset 148h
Input stream 7: offset 288h
Input stream 8: offset 2A8h
Input stream 9: offset 2C8h
Input stream 10: offset 2E8h
Input stream 11: offset 308h
Input stream 12: offset 328h
Input stream 13: offset 348h
Input stream 14: offset 368h
Output stream 0: offset 168h
Output stream 1: offset 188h
Output stream 2: offset 1A8h
Output stream 3: offset 1C8h
Output stream 4: offset 1E8h
Output stream 5: offset 208h
Output stream 6: offset 228h
output stream 7: offset 248h
Output stream 8: offset 268h
Output stream 9: offset 388h
Output stream 10: offset 3A8h
Output stream 11: offset 3C8h
Output stream 12: offset 3E8h
Output stream 13: offset 408h
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:0 | 00000000h | RW | Cyclic Buffer Length (CBL) Indicates the number of bytes in the complete cyclic buffer. CBL must represent an |