Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
PCH Power Management Status (PCH_PM_STS2) – Offset 1824
This register contains misc. fields used to record events pertaining to PCH power management. Unless otherwise indicated, all RWC bits are cleared with a write of '1' by software.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:15 | - | - | Reserved
|
14 | 0b | RW/1C/V | CPU Reset Done Failure (CRD) CPU Reset Done message did not arrive from the CPU. |
13 | 0b | RW/1C/V | ME Host Boot Prep Done Failure (ME_HBPD) ME Host Boot Preparation did not complete. |
12 | 0b | RW/1C/V | PINSTOP Acknowledge Failure (PINSTOP_ACK) The GbE PHY did not respond to the PINSTOP message. |
11 | - | - | Reserved
|
10 | 0b | RW/1C/V | SMT Reset Acknowledge Failure (SMT_RST_ACK) One or more SMT controllers did not respond to the CSME bus reset warning. |
9 | 0b | RW/1C/V | EXI State Transition Acknowledge Failure (EXI_STATE_TRANS_ACK) EXI state transition ACK did not arrive. |
8 | 0b | RW/1C/V | SPI Common Prep Handshake Failure (SPI_HRHS) The SPI controller did not complete the host partition reset/Sx entry handshake. |
7 | 0b | RW/1C/V | XCK Common Prep Handshake Failure (XCK_HRHS) The integrated clocking unit did not complete the host partition reset/Sx entry handshake. |
6 | 0b | RW/1C/V | CPU S345/Reset Warn Acknowledge Failure (CPU_S345RW_ACK) The CPU did not respond to the GO_S345 or RESET_WARN message. |
5 | 0b | RW/1C/V | CPU S1 Acknowledge Failure (CPU_S1_ACK) The CPU did not respond to the GO_S1_XXX message. |
4 | 0b | RW/1C/V | DMI L23 Entry Failure (DMI_L23) The DMI interface did not respond to the request to entry L23. |
3 | 0b | RW/1C/V | SMBus Host Reset Handshaking Failure (SMB_SRHS) The host SMBus controller did not complete the host partition reset handshake. |
2 | 0b | RW/1C/V | South Port L23 Entry Failure (SP_L23) The PCH PCI Express ports did not complete the host partition reset/Sx entry handshake. |
1 | 0b | RW/1C/V | XHCI Common Prep Handshake Failure (XHCI_HRHS) The XHCI controller did not complete the host partition reset/Sx entry handshake. |
0 | - | - | Reserved
|