DeepSx Configuration (DSX_CFG) – Offset 1834 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

DeepSx Configuration (DSX_CFG) – Offset 1834

This register contains misc. fields used to configure the PCH's power management behavior.

This register is in the RTC power well and is reset by RTCRST# assertion.

Bit Range	Default	Access	Field Name and Description
30:5	-	-	Reserved
4	0b	RW	Require CNV Wake Disabled for DeepSx Entry/SUSPWRDNACK (REQ_CNV_NOWAKE_DSX) If this bit is 0, the state of connectivity wake enable is not considered when making DeepSx entry decisions. If this bit is 1, connectivity wake must be disabled to allow DeepSx entry or SUSPWRDNACK assertion, and even then all other conditions must be satisfied.
3	0b	RW	Require BATLOW# Assertion for DeepSx Entry/SUSPWRDNACK (REQ_BATLOW_DSX) If this bit is 0, the state of the BATLOW# pin is not considered when making DeepSx entry and SUSPWRDNACK decisions. If this bit is 1, BATLOW# must be asserted to allow DeepSx entry or SUSPWRDNACK assertion, and even then all other entry conditions must be satisfied.
2	0b	RW	WAKE# Pin DeepSx Enable (WAKE_PIN_DSX_EN) When this bit is 1, the PCI Express WAKE# pin is monitored while in Deep Sx, supporting waking from Deep Sx due to assertion of this pin. In this case, the platform must externally pull up the pin to the DSW (instead of pulling up to the SUS as has historically been the case). When this bit is 0: - DeepSx enabled configurations: The PCH internal pull-down on the WAKE# pin is enabled in Deep Sx and during G3 exit and the pin is not monitored during this time. -Deep Sx disabled configurations: The PCH internal pull-down on the WAKE# pin is never enabled Note: Deep Sx disabled configurations must leave this bit at 0.
1	0b	RW	AC_PRESENT Pin Pulldown in DeepSx Disable (ACPRES_PD_DSX_DIS) When this bit is 1, the internal pull-down on the ACPRESENT pin is disabled. However, the pulldown is not necessarily enabled if the bit is '0'. This bit must be left at '0' for Deep Sx disabled configurations, and the pulldown is disabled for those configurations even though the bit is '0'. To support ME wakes from Deep Sx, the pin is always monitored regardless of the value of this host policy bit. When this bit is '0': DeepSx enabled configurations: The PCH internal pull-down on ACPRESENT is enabled in Deep Sx and during G3 exit. Deep Sx disabled configurations: The PCH internal pull-down on ACPRESENT is always disabled.
0	0b	RW	LANWAKE Pin DeepSx Enable (LANWAKE_PIN_DSX_EN) When this bit is 1, the LANWAKE pin is monitored while in DeepSx, supporting waking from DeepSx due to assertion of this pin. In this case, the platform must drive the pin to the correct value while in DeepSx. DeepSx disabled configurations must leave this bit at 0. When this bit is 0: DeepSx enabled configurations: The PCH internal pull-down on LANWAKE pin is enabled in deep-Sx and during G3 exit and the pin is not monitored during this time. DeepSx disabled configurations: The PCH internal pull-down is never enabled