Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0) – Offset 140
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_23) Applied to GPP_C23. Same description as bit 0. |
22 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_22) Applied to GPP_C22. Same description as bit 0. |
21 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_21) Applied to GPP_C21. Same description as bit 0. |
20 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_20) Applied to GPP_C20. Same description as bit 0. |
19 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_19) Applied to GPP_C19. Same description as bit 0. |
18 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_18) Applied to GPP_C18. Same description as bit 0. |
17 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_17) Applied to GPP_C17. Same description as bit 0. |
16 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_16) Applied to GPP_C16. Same description as bit 0. |
15 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_15) Applied to GPP_C15. Same description as bit 0. |
14 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_14) Applied to GPP_C14. Same description as bit 0. |
13 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_13) Applied to GPP_C13. Same description as bit 0. |
12 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_12) Applied to GPP_C12. Same description as bit 0. |
11 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_11) Applied to GPP_C11. Same description as bit 0. |
10 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_10) Applied to GPP_C10. Same description as bit 0. |
9 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_9) Applied to GPP_C9. Same description as bit 0. |
8 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_8) Applied to GPP_C8. Same description as bit 0. |
7 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_7) Applied to GPP_C7. Same description as bit 0. |
6 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_6) Applied to GPP_C6. Same description as bit 0. |
5 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_5) Applied to GPP_C5. Same description as bit 0. |
4 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_4) Applied to GPP_C4. Same description as bit 0. |
3 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_3) Applied to GPP_C3. Same description as bit 0. |
2 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_2) Applied to GPP_C2. Same description as bit 0. |
1 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_1) Applied to GPP_C1. Same description as bit 0. |
0 | 0b | RW/1C | GPI General Purpose Events Status (GPI_GPE_STS_GPPC_C_0) These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). |