PCI Express Replay Timer Policy 1 (PCIERTP1) – Offset 300 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

PCI Express Replay Timer Policy 1 (PCIERTP1) – Offset 300

The Replay Timer controlled by the Replay Timeout field is started when the Retry Buffer is empty and a TLP is placed into it or an Ack/Nak DLLP is received and there are still non-acknowledged packets within the Retry Buffer. The counter continues to count until the next valid Ack DLLP or a NAK DLLP that acknowledges unacknowledged TLPs is received, or it reaches the timeout value specified by this register. When a valid Ack/Nak DLLP is received, the timer is reset to zero and restarted if there are still non-acknowledged packets within the Retry Buffer. Otherwise if the Retry Buffer is empty, the counter is just reset to zero. If the timer reaches the timeout value, the non-acknowledged packets within the Retry Buffer will be replayed.

The default for this register is dependant on the MAX_PAYLOAD_SIZE , the NEGOTIATED_WIDTH, and the NEGOTIATED_SPEED.

Bit Range	Default	Access	Field Name and Description
30:24	-	-	Reserved
23:20	Ah	RW	Gen 2 x1 (G2X1) Gen 2 x1 (G2X1): Determines how many link clock cycles the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. The Replay Timeout value to be used varies based on the effective Maximum Payload Size. For 128B MPS: nnn * 64 link clocks. For 256B MPS: (nnn + 4) * 64 link clocks. For 512B MPS: (nnn + 7) * 64 link clocks. For PCIE Gen 2 speed and x1 width For Mobile Express HS-Gear 3 speed and x1 width.
19:16	6h	RW	Gen 2 x2 (G2X2) Gen 2 x2 (G2X2): Determines how many link clock cycles the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. The Replay Timeout value to be used varies based on the effective Maximum Payload Size. For 128B MPS: nnn * 64 link clocks. For 256B MPS: (nnn + 2) * 64 link clocks. For 512B MPS: (nnn + 4) * 64 link clocks. For PCIe Gen 2 speed and x2 width. For Mobile Express HS-Gear 3 speed and x2 width.
15:12	4h	RW	Gen 2 x4 (G2X4) Gen 2 x4 (G2X4): Determines how many link clock cycles the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. The Replay Timeout value to be used varies based on the effective Maximum Payload Size. For 128B MPS: nnn * 64 link clocks. For 256B MPS: (nnn + 2) * 64 link clocks. For 512B MPS: (nnn + 3) * 64 link clocks. For PCIe Gen 2 speed and x4 width. For Mobile Express HS-Gear 3 speed and x4 width.
11:8	Fh	RW	Gen 1 x1 (G1X1) Gen 1 x1 (G1X1): Determines how many symbol times (i.e. number of link clock cycles) the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. The Replay Timeout value to be used varies based on the effective Maximum Payload Size. For 128B MPS: nnn * 64 link clocks. For 256B MPS: (nnn + 10) * 64 link clocks. For 512B MPS: (nnn + 17) * 64 link clocks. For PCIe Gen 1 speed and x1 width. For Mobile Express HS-Gear 2 speed and x1 width.
7:4	9h	RW	Gen 1 x2 (G1X2) Gen 1 x2 (G1X2): Determines how many symbol times (i.e. number of link clock cycles) the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. The Replay Timeout value to be used varies based on the effective Maximum Payload Size. For 128B MPS: nnn * 64 link clocks. For 256B MPS: (nnn + 4) * 64 link clocks. For 512B MPS: (nnn + 8) * 64 link clocks. For PCIe Gen 1 speed and x2 width. For Mobile Express HS-Gear 2 speed and x2 width.
3:0	6h	RW	Gen 1 x4 (G1X4) Gen 1 x4 (G1X4): Determines how many symbol times (i.e. number of link clock cycles) the Data Link Layer will wait to replay the contents of the Retry Buffer if a valid Ack/Nak DLLP is not received. The Replay Timeout value to be used varies based on the effective Maximum Payload Size. For 128B MPS: nnn * 64 link clocks. For 256B MPS: (nnn + 2) * 64 link clocks. For 512B MPS: (nnn + 3) * 64 link clocks. For PCIe Gen 1 speed and x4 width. For Mobile Express HS-Gear 2 speed and x4 width.