Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
Block Gap Control Register (blockgapcontrol) – Offset 2a
This register is used to program the block gap request, read wait control and interrupt at blockgap.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7 | 1h | RW | Boot Acknowledge Check (boot_ack_chk) To check for the boot acknowledge in boot operation. |
6 | 0h | RW | Alternate Boot Enable (alt_boot_en) To start boot code access in alternative mode. |
5 | 0h | RW | Boot Code Access (BOOT_EN) To start boot code access |
4 | 0h | RW | SPI mode enable (spi_mode) SPI mode enable bit. |
3 | - | - | Reserved
|
2 | 0h | RW | Read Wait Control (rd_wait_ctrl) The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects a card insertion, it shall set this bit according to the CCCR of the card. If the card does not support read wait, this bit shall never be set to 1 otherwise DAT line conflict may occur. If this bit is set to 0, Suspend / Resume cannot be supported |
1 | 0h | RW | Continue Request (continue_req) This bit is used to restart a transaction which wasstopped using the Stop At Block Gap Request. To cancelstop at the block gap, set Stop At block Gap Request to0 and set this bit to restart the transfer. |
0 | 0h | RW | Stop At Block Gap Request (stopatblkgap_req) This bit is used to stop executing a transaction at thenext block gap for non- DMA,SDMA and ADMA transfers.Until the transfer complete is set to 1, indicating atransfer completion the HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request andContinue Request shall not cause the transaction torestart. |