Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
HPET Memory Mapped Registers
The timer registers are memory mapped directly (rather than indexed) to allow the CPU to access each register without having to use an index register. This ensures accesses are safe for multi-threaded environments. The timer register space is 1024 bytes. The registers are generally aligned on 64-bit boundaries to simplify implementation with IA64 processors.In the PCH, there are 4 possible memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3) FED0_2000h, 4) FED0_3000h. The choice of address range should be selected by assigning the High Performance Event Timer Configuration (HPTC) register fields in the configuration space of the Primary to Sideband Bridge. All registers are implemented in the Primary power well, and all bits are reset by PLTRST#. Reads to reserved registers or bits will return a value of 0.
Behavorial Rules:
1. Software can read or write the various bytes in these registers using 32-bit or 64-bit accesses. Software must not attempt to read or write across register boundaries. Forexample, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accessesshould not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh.Any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. However, these accesses should not result in system hangs. 64-bit accesses can only be to x0h and must not cross 64-bit boundaries.
2. Software should not write to read-only registers.
3. Software should not expect any particular or consistent value when readingreserved registers or bits.
Offset | Size (Bytes) | Register Name (Register Symbol) | Default Value |
---|---|---|---|
fed00000h | 8 | 27BC86B8086A701h | |
fed00010h | 8 | 0h | |
fed00020h | 8 | 0h | |
fed000f0h | 8 | 0h | |
fed00100h | 8 | 0h | |
fed00108h | 8 | FFFFFFFFFFFFFFFFh |