Input/Output Stream Descriptor x FIFO Size (ISD0FIFOS) – Offset 90 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Input/Output Stream Descriptor x FIFO Size (ISD0FIFOS) – Offset 90

NOTE: This register applies to the following input and output streams at the corresponding offsets:

Input stream 0: offset 90h

Input stream 1: offset B0h

Input stream 2: offset D0h

Input stream 3: offset F0h

Input stream 4: offset 110h

Input stream 5: offset 130h

Input stream 6: offset 150h

Input stream 7: offset 290h

Input stream 8: offset 2B0h

Input stream 9: offset 2D0h

Input stream 10: offset 2F0h

Input stream 11: offset 310h

Input stream 12: offset 330h

Input stream 13: offset 350h

Input stream 14: offset 370h

Output stream 0: offset 170h

Output stream 1: offset 190h

Output stream 2: offset 1B0h

Output stream 3: offset 1D0h

Output stream 4: offset 1F0h

Output stream 5: offset 210h

Output stream 6: offset 230h

output stream 7: offset 250h

Output stream 8: offset 270h

Output stream 9: offset 390h

Output stream 10: offset 3B0h

Output stream 11: offset 3D0h

Output stream 12: offset 3F0h

Output stream 13: offset 410h

Output stream 14: offset 430h

Bit Range	Default	Access	Field Name and Description
15:0	0000h	RW/V	FIFO Size (FIFOS) When GCAP2.EEAC = 0, indicates the maximum number of bytes that could be evicted (for input) or fetched (for output) by the controller at one time. This is the maximum number of bytes that may have been received into the HW buffer but not yet transferred out, and is also the maximum possible value that the PICB count will increase by at one time. The FIFO size is calculated based on the stream format programmed in (I/O)SDxFMT register, the min frame of buffering setting in EM(3/4)(SEM(3/4)).(I/O)SBSMFA[1:0] field, and the minimum buffer size threshold setting in EM2.BSMT[1:0] field. As the default value is zero, SW must write to the (I/O)SDxFMT register to kick off the FIFO size calculation, and read back to find out the HW allocated FIFO size. When GCAP2.EEAC = 1, this FIFOS value represent the minimum FIFO size HW required to operate efficiently. SW can program FIFOL register to extend the effective FIFO size in HW beyond this minimum value advertised. In this case, the maximum number of bytes that could be evicted (for input) or fetched (for output) by the controller at one time, the maximum number of bytes that may have been received into the HW buffer but not yet transferred out, and also the maximum possible value that the PICB count will increase by one time, all these maximum value could be larger than FIFOS value, depending on the FIFOL register setting. When EM2.HWFIFOL = 1, this FIFOS value will reflect the larger FIFO size of up to 10 ms, if extra buffer space is available.

Bit Range

Default

Access

Field Name and Description

15:0

0000h

RW/V

FIFO Size (FIFOS)

When GCAP2.EEAC = 0, indicates the maximum number of bytes that could be

evicted (for input) or fetched (for output) by the controller at one time.

This is the maximum number of bytes that may have been received into the

HW buffer but not yet transferred out, and is also the maximum possible

value that the PICB count will increase by at one time.

The FIFO size is calculated based on the stream format programmed in

(I/O)SDxFMT register, the min frame of buffering setting in

EM(3/4)(SEM(3/4)).(I/O)SBSMFA[1:0] field, and the

minimum buffer size threshold setting in EM2.BSMT[1:0] field.

As the default value is zero, SW must write to the (I/O)SDxFMT register

to kick off the FIFO size calculation, and read back to find out the HW

allocated FIFO size.

When GCAP2.EEAC = 1, this FIFOS value represent the minimum FIFO size HW

required to operate efficiently. SW can program FIFOL register to extend

the effective FIFO size in HW beyond this minimum value advertised. In

this case, the maximum number of bytes that could be evicted (for input)

or fetched (for output) by the controller at one time, the maximum number

of bytes that may have been received into the HW buffer but not yet

transferred out, and also the maximum possible value that the PICB count

will increase by one time, all these maximum value could be larger than

FIFOS value, depending on the FIFOL register setting.

When EM2.HWFIFOL = 1, this FIFOS value will reflect the larger FIFO size

of up to 10 ms, if extra buffer space is available.