Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Timer Control Word Register (TCW) – Offset 43
This register is programmed prior to any counter being accessed to specify counter modes. Following reset, the control words for each register are undefined and each counter output is 0. Each timer must be programmed to bring it into a known state.
There are two special commands that can be issued to the counters through this register, the Read Back Command and the Counter Latch Command. When these commands are chosen, several bits within this register are redefined.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7:6 | 00b | WO | Counter Select (CNT_SLT) The Counter Selection bits select the counter the control word acts upon as shown below. The Read Back Command is selected when bits[7:6] are both 1 |
5:4 | 00b | WO | Read/Write Select: (RW_SLT) These bits are the read/write control bits. The actual counter programming is done through the counter port (40h for counter 0 and 42h for counter 2) |
3:1 | 000b | WO | Counter Mode Selection (CNT_MD_SLTN) These bits select one of six possible modes of operation for the selected counter. |
0 | 0b | WO | Binary/BCD Countdown Select (B_BCD_CNTDWN_SLT) 0 Binary countdown is used. The largest possible binary count is 2^16 |