Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Interrupt Status (INTSTS) – Offset 24
GIS and CIS bits are not affected by controller reset.
The number of SIS bits in this register is depending on the total number of stream DMA implemented.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RO/V | Global Interrupt Status (GIS) This bit is an OR of all of the interrupt status bits in this register and PPSTS register |
30 | 0b | RW/V | Controller Interrupt Status (CIS) Status of general controller interrupt. A 1 indicates that an interrupt condition occurred due to a Response Interrupt, a Response Buffer Overrun Interrupt, CORB Memory Error Interrupt, or a SDIN State Change event. The exact cause can be determined by interrogating other registers. |
29:16 | - | - | Reserved
|
15:0 | 0h | RW/V | Stream Interrupt Status (SIS) A 1 indicates that an interrupt condition occurred on the corresponding Stream. |