Debug Capability Control Register (DCCTRL) – Offset 8720 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Debug Capability Control Register (DCCTRL) – Offset 8720

Bit Range	Default	Access	Field Name and Description
31	0b	RW	Debug Capability Enable (DCE) Default = 0. Setting this bit to a ‘1’ enables xHCI USB Debug Capability operation. This bit is a ‘0’ if the USB Debug Capability is disabled. Clearing this bit releases the Root Hub port assigned to the Debug Capability, and terminates any Debug Capability Transfer or Event Ring activity. <br>Note that DCE may be cleared to ‘0’ by the assertion of a reset condition.
30:24	00h	RO	Device Address (DADDR) Default = 0. This field reports the USB device address assigned to the Debug Device during the enumeration process. This field is valid when the DbC Run bit is ‘1’.
23:16	00h	RO	Debug Max Burst Size (DMBS) Default = xHC Vendor defined. This field identifies the maximum burst size supported by the bulk endpoints of this DbC implementation.
15:5	-	-	Reserved
4	0b	RW/1C	DbC Run Change (DRC) Default = 0. This bit shall be set to '1' when DCR bit is cleared to '0', i.e. by any DbC Port State transition that exits the DbC-Configured state. While this bit is ‘1’ the Debug Capability Doorbell Register (DCDB) is disabled. Software shall clear this bit to re-enable the DCDB.
3	0b	RW/1S	Halt IN TR (HIT) Default = 0. While this bit is ‘1’ the Debug Capability shall generate STALL TPs for all OUT DPs received for the IN TR. The Debug Capability shall clear this bit when a ClearFeature(ENDPOINT_HALT) request is received for the endpoint. This field is valid only when the Debug Capability is in Run Mode (DCR = ‘1’). When not in Run Mode, this field shall return ‘0’ when read, and writes will have no effect.
2	0b	RW/1S	Halt OUT TR (HOT) Default = 0. While this bit is ‘1’ the Debug Capability shall generate STALL TPs for all IN TPs received for the OUT TR. The Debug Capability shall clear this bit when a ClearFeature(ENDPOINT_HALT) request is received for the endpoint. This field is valid only when the Debug Capability is in Run Mode (DCR = ‘1’). When not in Run Mode, this field shall return ‘0’ when read, and writes will have no effect.
1	0b	RW	Link Status Event Enable (LSE) Default = ‘0’. Setting this bit to a ‘1’ enables the Debug Capability to generate Port Status Change Events due the Port Link Status Change bit transitioning from a ‘0’ to a ‘1’.
0	0b	RO	DbC Run (DCR) . Default = 0. When ‘0’, Debug Device is not in the Configured state. When ‘1’, Debug Device is in the Configured state and bulk Data pipe transactions are accepted by Debug Capability and routed to the IN and OUT Transfer Rings. A ‘0’ to ‘1’ transition of the Port Reset (DCPORTSC:PR) bit will clear this bit to ‘0’.