Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
Uncorrectable Error mask Register (CNVI_WIFI_UNCORRECT_ERR_MASK) – Offset 108
Bits in this register are of type RWS - if set to 1 the error is not logged in the Header Log register, or does not update the First Error Pointer and is not reported to PCI Express Root Complex.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:21 | - | - | Reserved
|
20 | 0x0 | RW | Unsupported Request Error Mask (UNSPR_REQ_ERR_MSK) Sticky value. |
19 | 0x0 | RO | ECRC Error mask (ECRC_ERR_MSK_19) Not implemented. |
18 | 0x0 | RW | Malformed TLP Mask (MAL_TLP_MSK) Sticky value. |
17 | 0x0 | RW | Receiver Overflow Mask (REC_OVRF_MSK) Sticky value. |
16 | 0x0 | RW | Unexpected Completion Mask (UNXPL_COM_MSK) Sticky value. |
15 | 0x0 | RW | Completer Abort Mask (COM_AB_MSK) Sticky value. |
14 | 0x0 | RW | Completion Timeout Mask (COM_TO_MSK) Sticky value. |
13 | 0x0 | RW | Flow Control Protocol Error Mask (FLWCNT_PR_MSK) Sticky value. |
12 | 0x0 | RW | Poisoned TLP Mask (POIS_TLP_MSK) Sticky value. |
11:5 | - | - | Reserved
|
4 | 0x0 | RW | Header Log (DLNK_PRERR_MSK) Does not update the First Error Pointer and is not Data Link Protocol Error Mask, if set to 1 the error is not logged in the Header. Sticky value |
3:1 | - | - | Reserved
|
0 | 0x0 | RO | Training Error Mask (TRNG_ERR_MSK_0) Not implemented. |