Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Power Management Control and Status Register (PMECTRLSTATUS) – Offset 84
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:16 | - | - | Reserved
|
15 | 0h | RW/1C | PME Status (PMESTATUS) 0: Software clears the bit by writing a 1 to it. |
14:9 | - | - | Reserved
|
8 | 0h | RW | PME Enable (PMEENABLE) 1: Enables the function to assert PME#. |
7:4 | - | - | Reserved
|
3 | 1h | RO | (NO_SOFT_RESET) This bit indicates that devices transitioning from D3hot to D0 because ofPowerstate commands do not perform an internal reset.Configuration Context is preserved. |
2 | - | - | Reserved
|
1:0 | 0h | RW | Power State (POWERSTATE) This field is used both to determine the current power state and to set a newpower state.The values are: |