Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
NMI Enable (GPI_NMI_EN_GPP_B_0) – Offset 1e4
Register bits in this register are implemented for GPP_B signals that have NMI capability only. Other bits are reserved and RO.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23 | 0b | RW | GPI NMI Enable (GPI_NMI_EN_GPPC_B_23) Same description as bit 14. |
22:21 | - | - | Reserved
|
20 | 0b | RW | GPI NMI Enable (GPI_NMI_EN_GPPC_B_20) Same description as bit 14. |
19:15 | - | - | Reserved
|
14 | 0b | RW | GPI NMI Enable (GPI_NMI_EN_GPPC_B_14) This bit is used to enable/disable the generation of NMI when thecorresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. |
13:0 | - | - | Reserved
|