Command Ring Low (CRCR_LO) – Offset 98 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Command Ring Low (CRCR_LO) – Offset 98

Bit Range	Default	Access	Field Name and Description
31:6	0000000h	WO	Command Ring Pointer (CRP) This field defines low order bits of the initial value of the 64-bitCommand Ring Dequeue Pointer. Notes: 1. Writes to this field are ignored when Command Ring Running bit (CRR) = 1b. 2. If the CRCR register is written while the Command Ring is stopped (CRR = 0b), the value ofthis field shall be used to fetch the first Command TRB the next time the Host ControllerDoorbell register is written with the DB Reason field set to Host Controller Command. 3. If the CRCR register is not written while the Command Ring is stopped (CRR = 0b), then theCommand Ring shall begin fetching Command TRBs at the current value of the internal xHCCommand Ring Dequeue Pointer. 4. Reading this field always returns 0b.
5:4	-	-	Reserved
3	0b	RO	Command Ring Running (CRR) This bit is set to 1b if the Run/Stop (R/S) bit is 1b and theHost Controller Doorbell register is written with the DB Reason field set to Host ControllerCommand. It is cleared to 0b when the Command Ring is stopped after writing a 1b to theCommand Stop (CS) or Command Abort (CA) bits, or if the R/S bit is cleared to 0b.
2	0b	WO	Command Abort (CA) Writing a 1b to this bit shall immediately terminate the currentlyexecuting command, stop the Command Ring, and generate a Command Completion Event with theCompletion Code set to Command Ring Stopped. The next write to the Host Controller Doorbell with DB Reason field set to Host Controller Commandshall restart the Command Ring operation. Notes: 1. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) = 0b. 2. Reading this bit always returns 0b.
1	0b	WO	Command Stop (CS) Writing a 1b to this bit shall stop the operation of the Command Ringafter the completion of the currently executing command, and generate a Command CompletionEvent with the Completion Code set to Command Ring Stopped and the Command TRB Pointer setto the current value of the Command Ring Dequeue Pointer. The next write to the Host Controller Doorbell with DB Reason field set to Host Controller Commandshall restart the Command Ring operation. Notes: 1. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) bit = 0b. 2. Reading this bit always returns 0b.
0	0b	WO	Ring Cycle State (RCS) This bit identifies the value of the xHC Consumer Cycle State (CCS)flag for the TRB referenced by the Command Ring Pointer. Notes: 1. Writes to this bit are ignored when the Command Ring Running (CRR) bit = 1b. 2. If the CRCR register is written while the Command Ring is stopped (CCR = 0b), then the valueof this flag shall be used to fetch the first Command TRB the next time the Host ControllerDoorbell register is written with the DB Reason field set to Host Controller Command. 3. If the CRCR register is not written while the Command Ring is stopped (CCR = 0b), then theCommand Ring will begin fetching Command TRBs using the current value of the internalCommand Ring CCS flag. 4. Reading this flag always returns 0b.