Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Clock Gating Control (CGCTL) – Offset 48
The trunk clock gating enable and local clock gating enables are meant for BIOS or driver to enable or disable the HW capability to detect idle condition and clock gate accordingly. HW should treat these clock gate enable register bits as 0 if FNCFG.CGD = 1.
Note that the clock gating will only be initiated when out of platform reset, if conditions are met.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:21 | - | - | Reserved
|
20 | 1b | RW | IOSF Sideband Trunk Gate Enable (IOSFSTCGE) Enable IOSF trunk clock gating functionality on IOSF interface. When |
19 | 1b | RW | IOSF Backbone Trunk Gate Enable (IOSFBTCGE) Enable IOSF trunk clock gating functionality on IOSF interface. When |
18 | - | - | Reserved
|
17 | 1b | RW | XTAL Oscillator Trunk Clock Gating Enable (XOTCGE) Set to 1 to enable trunk clock gating. If enabled, HW will trunk clock |
16 | 1b | RW | Audio PLL Trunk Clock Gating Enable (APTCGE) Set to 1 to enable trunk clock gating. If enabled, HW will trunk clock |
15:9 | - | - | Reserved
|
8 | 1b | RW | IOSF Sideband Dynamic Clock Gate Enable (IOSFSDCGE) Enable IOSF dynamic clock gating functionality inside IOSF interface. |
7 | 1b | RW | IOSF Backbone Dynamic Clock Gate Enable (IOSFBDCGE) Enable IOSF dynamic clock gating functionality inside IOSF interface. |
6 | 1b | RW | Miscellaneous Backbone Dynamic Clock Gating Enable (MISCBDCGE) This controls dynamic clock gating of backbone (Command/data) clocks to |
5 | 1b | RW | IDMA Backbone Dynamic Clock Gating Enable (IDMABDCGE) This controls dynamic clock gating of backbone (Command/data) clocks to |
4 | 1b | RW | ODMA Backbone Dynamic Clock Gating Enable (ODMABDCGE) This controls dynamic clock gating of backbone (Command/data) clocks to |
3 | 1b | RW | HD Audio Link Dynamic Clock Gating Enable (HDALDCGE) This controls dynamic clock gating of bitclk to Link Layer and each |
2:1 | - | - | Reserved
|
0 | 1b | RW | Memory Dynamic Clock Gating Enable (MEMDCGE) When set to 1, it allows HW to automatically detect for idle condition |