30:29 | - | - | Reserved |
28 | 0b | RW | Slave Host Reset Ack Override (SLV_HOST_RST_ACK_OVRD) A 1 in this bit will cause the eSPI-MC to not wait for theSlave HOST_RESET_ACK Virtual Wire before (immediately) asserting the ResetPrepAck(Host space, GenPrep). The Host_Reset_Warn VW will be transmitted to the Slaveindependent of the setting for this bit. |
27:26 | 0b | RW | Peripheral Channel Received Master or Target Abort Reporting Enable (PCRMTARE) 00: Disable RMA or RTA Reporting 01: Reserved 10: Enable RMA or RTA Reporting as SERR 11: Enable RMA or RTA Reporting as SMI Note: SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# isdeasserted. Note: SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted. |
25 | 0b | RW | Peripheral Channel Unsupported Request Reporting Enable (PCURRE) If set to 1 bysoftware, it allows reporting of an Unsupported Request (UR) as a System Error (SERR). If eSPI controller decodes a Posted transaction that is not supported, it sets the PCURD bit. If PCCMD.SEE (SERR enable) is also set to 1, then eSPIMCsets the PCSTS.SSE (Signaled System Error) bit and sends a Do_SErr message. Note: If the transaction was a Non-Posted request, then the agent handles thetransaction as an Advisory Non-Fatal error, and no error logging or signaling is done. The Completion with UR Completion Status serves the purpose of error reporting. |
24 | 0b | RW/1C/V | Peripheral Channel Unsupported Request Detected (PCURD) Set to 1 by hardwareupon detecting an Unspported Request (UR) that is not considered an Advisory Non-Fatal error and PCERR.PCURRE is set. Cleared to 0 when software writes a 1 to thisregister. |
23:15 | - | - | Reserved |
14:13 | 0b | RW | Peripheral Channel Non-Fatal Error Reporting Enable (PCNFEE) 00: Disable Non-Fatal Error Reporting 01: Reserved 10: Enable Non-Fatal Error Reporting as SERR 11: Enable Non-Fatal Error Reporting as SMI Note: SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# isdeasserted. Note: SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted. Note: SMI/SERR messages are not generated if the Host is in reset (PLTRST# asserted). |
12 | 0b | RW/1C/V | Peripheral Channel Non-Fatal Status (PCNFES) This field is set by hardware if a Non-Fatal Error condition is detected on the Peripheral Channel. Software must clearthis bit. 0: No Non-Fatal Error detected 1: Non-Fatal Error detected (PCNFEC has a non-zero value) Note: Clearing this unlocks the PCNFEC field and triggers a SB Deassert_SMImessage if PCNFEE is set to SMI. Note: Setting of this bit is independent of the enable to generate a SMI/SERR (PCNFEE) |
11:8 | 0b | RO/V | Peripheral Channel Non-Fatal Cause (PCNFEC) 0h: No error 1h: Slave Response Code: NONFATAL_ERROR 2h: Slave Response Code: Unsuccessful Completion 3h: Unexpected completion received from Slave (i.e. completion without non-postedrequest or completion with invalid tag or completion with invalid length) 4h: Unsupported Cycle Type (w.r.t. Command) 5h: Unsupported Message Code 6h: Unsupported Address/Length alignment (upstream only): Memory: Address +Length > 64 B (aligned) [for both Posted and Non-Posted transactions] 7h: Unsupported Address/Length alignment (upstream only): Memory: 64-bit Addresswith Addr[63:32] = 0h [for both Posted and Non-Posted transactions] 8h – Fh: Reserved Note: This field is updated after a Peripheral channel transaction is completed if the PCNFES bit is not set. |
7 | - | - | Reserved |
6:5 | 0b | RW | Peripheral Channel Fatal Error Reporting (PCFEE) 00: Disable Fatal Error Reporting 01: Reserved 10: Enable Fatal Error Reporting as SERR (IOSF-SB Do_SErr message) 11: Enable Fatal Error Reporting as SMI (IOSF-SB Assert_SMI message) Note: SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# isdeasserted. Note: SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted. Note: SMI/SERR messages are not generated if the Host is in reset (PLTRST# asserted). |
4 | 0b | RW/1C/V | Peripheral Channel Fatal Error Reporting (PCFES) This field is set by hardware if a FatalError condition is detected on the Peripheral Channel. Software must clear this bit by writing a 1 to it. 0: No Fatal Error detected 1: Fatal Error Type 2 detected (PCFEC has a non-zero value) Note: Clearing this unlocks the PCFEC field and triggers an SB Deassert_SMImessage if PCFEE is set to SMI. Note: Setting of this bit is independent of the enable to generate a SMI/SERR (PCFEE). |
3:0 | 0b | RO/V | Peripheral Channel Fatal Error Cause (PCFEC) 0h: No error 1h – 7h: Reserved 8h: Malformed Slave Response Payload: Payload length > Max Payload Size (aligned)[Type 2] 9h: Malformed Slave Response Payload: Read request size > Max Read Request Size(aligned) [Type 2] Ah: Malformed Slave Response Payload: Address + Length > 4KB (aligned) [Type 2] Bh – Fh: Reserved Note: This field is updated after a Peripheral channel transaction is completed if the PCFES bit is not set. |