Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
GPIO Serial Blink Command/Status (GP_SER_CMDSTS) – Offset 210
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:24 | - | - | Reserved
|
23:22 | 00b | RW | Data Length Select (DLS) This read/write field determines the number of bytes to serialize on GPIO 00: Serialize bits 7:0 of GP_GB_DATA (1 byte) |
21:16 | 08h | RW | Data Rate Select (DRS) This read/write field selects the number of 166.64ns (4 clock periods GPIO clock - if GPIO clock is 24MHz) time intervals to count between Manchester data transitions. The default of 8h results in a 1333.33 ns minimum time between transitions. A value of 0h in this register produces undefined behavior. Software should not modify the value in this register unless the Busy bit is clear. |
15:9 | - | - | Reserved
|
8 | 0b | RO/V | Busy (BUSY) This read-only status bit is the hardware indication that a serialization is in progress. Hardware sets this bit to 1 based on the Go bit being set. Hardware clears this bit when the Go bit is cleared by the hardware. |
7:1 | - | - | Reserved
|
0 | 0b | RW | Go (GO) This bit is set to 1 by software to start the serialization process. Hardware clears the bit after the serialized data is sent. Writes of 0 to this register have no effect. Software should not write this bit to 1 unless the Busy status bit is cleared. |