PMSYNC Thermal Power Reporting Configuration (PMSYNC_TPR_CFG) – Offset 18c4 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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PMSYNC Thermal Power Reporting Configuration (PMSYNC_TPR_CFG) – Offset 18c4

This register contains configuration bits that apply to PCH reporting of thermal and power status to the Processor.

Power Well: Primary.

Bit Range	Default	Access	Field Name and Description
31	0b	RW/L	PCH-to-CPU Thermal Power Reporting Configuration Lockdown (PCH2CPU_TPR_CFG_LOCK) When set to 1b, this bit prevents writes from changing the value of this 32-bit register.
30:27	-	-	Reserved
26	0b	RW/L	PCH-to-CPU Thermal Throttle Enable (PCH2CPU_TT_EN) When this bit is set to '1' the PCH is enabled to set the thermal throttle request to the PROC using the PMSYNC PCH_THERM_STATUS bit. When this bit is '0', the PCH-to-CPU Thermal Throttling request is disabled.
25:24	00b	RW/L	PCH-to-CPU Thermal Throttle State (PCH2CPU_TT_STATE) This field specifies the PCH T-State level at which the PMC asserts the Thermal Throttle (PCH_THERM_STATUS) bit to the PROC. The PMC requests thermal throttling when the T-State, which is reported from the Thermal Sensor cluster, is greater than or equal to this state. Note: Refer to BIOS specification on the supported setting.
23:0	-	-	Reserved

PM_SYNC Miscellaneous Configuration (PM_SYNC_MISC_CFG)

Chipset Initialization Register C0 (CIRC0) PM_SYNC Miscellaneous Configuration (PM_SYNC_MISC_CFG)