Global SoC Bus Configuration 0 (GSBUSCFG0) – Offset c100 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Global SoC Bus Configuration 0 (GSBUSCFG0) – Offset c100

Bit Range	Default	Access	Field Name and Description
30:12	-	-	Reserved
11	0h	RW	Data Access is Big-Endian (DATBIGEND) This bit controls the endian modefor data accesses. 0: Little-endian (default) 1: Big-endian In big-endian mode, DMAaccess (both read and write) for packet data will utilize a Byte Invariant Big-Endianmode. Note: Since AXI requires byteinvariant endianness, settingDescBigend and DatBigEnd to one causes an address invariant transform to be applied,which is not appropriate. See section 9.3 and 9.4 of the AMBA AXI Specification. Hencefor an AXI master (DWC_USB3_MBUS_TYPE=1), this bit must be set to zero.
10:8	-	-	Reserved
7	0h	RW	INCR256 Burst Type Enable (INCR256BRSTENA) If software set this bit to “1”, the master uses INCR to do the 256-beat burst.
6	0h	RW	INCR128 Burst Type Enable (INCR128BRSTENA) If software set this bit to “1”, the master uses INCR to do the 128-beat burst.
5	0h	RW	INCR64 Burst Type Enable (INCR64BRSTENA) If software set this bit to “1”, the master uses INCR to do the 64-beat burst.
4	0h	RW	INCR32 Burst Type Enable (INCR32BRSTENA) If software set this bit to “1”, the master uses INCR to do the 32-beat burst.
3	0h	RW	INCR16 Burst Type Enable (INCR16BRSTENA) If software set this bit to "1", the master uses INCR to do the 16-beat burst.
2	1h	RW	INCR8 Burst Type Enable (INCR8BRSTENA) if software set this bit to "1", the master uses INCR to do the 8-beat burst
1	1h	RW	INCR4 Burst Type Enable (INCR4BRSTENA) When this bit is enabled the controller is allowed to do bursts of beat length 1, 2, 3, and 4
0	0h	RW	Undefined Length INCR Burst Type Enable (INCRBrstEna) Input to BUS-GM (INCRBRSTENA) When enabled, this has higher priority than other burst types. For the AHBconfiguration. if this bit is set to 1, AHB master tries to do only one INCR burst for eachtransfer unless it has to break it at a 1Kbyte boundary. If this bit is set to 0, the AHBmaster may still use INCR burst type at the beginning and end bursts of transfers toalign the address. The middle bursts are INCR4/8/16, depending when the type isenabled.