Slave Command Register (SCMD) – Offset 11 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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8254 Timer
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xHCI Memory Mapped

Slave Command Register (SCMD) – Offset 11

All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll the register until a write takes effect before assuming that a write has completed internally. Also, software must confirm the prior written value before writing to the register again.

Bit Range	Default	Access	Field Name and Description
6:3	-	-	Reserved
2	0b	RW	SMBALERT_DIS (SMB_D) Software sets this bit to 1 to block the generation of the interrupt or SMI# due to the SMBALERT# source. This bit is logically inverted and ANDed with the SMBALERT_STS bit. The resulting signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the wake logic.
1	0b	RW	HOST_NOTIFY_WKEN (HNW) Software sets this bit to 1 to enable the reception of a Host Notify command as a wake event. When enabled this event is ORed in with the other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register.
0	0b	RW	HOST_NOTIFY_INTREN (HNI) Software sets this bit to 1 to enable the generation of interrupt or SMI# when HOST_NOTIFY_STS is 1. This enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQB or SMI# is generated, depending on the value of the SMB_SMI_EN bit (D31, F3, Off40h, B1). If the HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or SMI#) is logically generated by ANDing the STS and INTREN bits.

Notify Device Address Register (NDA)

Slave Status Register (SSTS) Notify Device Address Register (NDA)