STET (STET) – Offset a0 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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STET (STET) – Offset a0

Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits(FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TXempty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active.

Bit Range	Default	Access	Field Name and Description
30:2	-	-	Reserved
1:0	0h	RW	stet (stet) Shadow TX Empty Trigger: This is a shadow register for the TX empty trigger bits(FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated.165This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full

Bit Range

Default

Access

Field Name and Description

30:2

Reserved

1:0

stet (stet)

Shadow TX Empty Trigger: This is a shadow register for the TX empty trigger bits(FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated.165This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported:

00 = FIFO empty

01 = 2 characters in the FIFO

10 = FIFO ¼ full

11 = FIFO ½ full

HTX (HTX)

SRT (SRT) HTX (HTX)