Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Mask for Transfer Interrupts (MaskTfr) – Offset b10
The contents of the Raw Status registers are masked with the contents of the
Mask registers: MaskBlock, MaskDstTran, MaskErr, MaskSrcTran, and MaskTfr.
Each Interrupt Mask register has a bit allocated per channel, for example,
MaskTfr(2) is the mask bit for the Channel 2 transfer complete interrupt.
When the source peripheral of DMA channel i is memory, then the source transaction
complete interrupt, MaskSrcTran(i), must be masked to prevent an erroneous triggering
of an interrupt on the int_combined signal. Similarly, when the destination peripheral
of DMA channel i is memory, then the destination transaction complete interrupt,
MaskDstTran(i), must be masked to prevent an erroneous triggering of an interrupt
on the int_combined(_n) signal.
A channel INT_MASK bit will be written only if the corresponding mask write enable
bit in the INT_MASK_WE field is asserted on the same OCP write transfer. This allows
software to set a mask bit without performing a read-modified write operation.
For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr(0),
while MaskTfr(7:1) remains unchanged. Writing hex 00xx leaves MaskTfr(7:0) unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus
allowing the DMA to set the appropriate bit in the Status registers and int_* port
signals.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:10 | - | - | Reserved
|
9:8 | 0h | WO | Interrupt Mask Write Enable (INT_MASK_WE) 0 = write disabled |
7:2 | - | - | Reserved
|
1:0 | 0h | RW | Interrupt mask (INT_MASK) 0-mask |