Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
I2C High Speed Master Mode Code Address (IC_HS_MADDR) – Offset c
I2C High Speed Master Mode Code Address Register. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30:3 | - | - | Reserved
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2:0 | 1h | RW | High Speed Mode Master Code (IC_HS_MAR) This bit field holds the value of the I2C HS mode master code. HS-mode master codes are reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each master has its unique master code; up to eight highspeed mode masters can be present on the same I2C bus system. Valid values are from 0 to 7. This register goes away and becomes read-only returning 0s if the IC_MAX_SPEED_MODE configuration parameter is set to either Standard (1) or Fast (2). |