HBA Capabilities (GHC_CAP) – Offset 0 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

HBA Capabilities (GHC_CAP) – Offset 0

This register indicates basic capabilities of the HBA to driver software. The RWO bits in this register are only cleared upon PLTRST#. This register is not reset by FLR.

Bit Range	Default	Access	Field Name and Description
31	1h	RW/O	Supports 64-bit Addressing (S64A) Indicates that the SATA controller can access 64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each PRD entry are read/write.
30	1h	RW/O	Supports Native Command Queuing Acceleration (SCQA) When set to 1, indicates that the SATA controller supports SATA command queuing using the DMA Setup FIS. The PCH handles DMA Setup FISes natively, and can handle auto-activate optimization through that FIS.
29	1h	RW/O	Supports SNotification Register (SSNTF) When set to 1, indicates the SATA controller supports the PxSNTF (SNotification) register and its associated functionality. When cleared to 0, the SATA controller does not support the PxSNTF (SNotification) register and its associated functionality.
28	1h	RW/O	Supports Mechanical Presence Switch (SMPS) When set to 1, indicates whether the SATA controller supports mechanical presence switches on its ports for use in hot-plug operations. This value is loaded by platform BIOS prior to operating system initialization. If this bit is set, BIOS must also map the SATAGP pins to the SATA controller through GPIO space.
27	1h	RW/O	Supports Staggered Spin-up (SSS) Indicates whether the SATA controller supports staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by platform BIOS prior to OS initialization. 0 = Staggered spin-up not supported. 1 = Staggered spin-up supported.
26	1h	RW/O	Supports Aggressive Link Power Management (SALP) 0 = Software shall treat the PxCMD.ALPEand PxCMD.ASP bits as reserved. 1 = The SATA controller supports auto-generating link requests to the partial or slumber states when there are no commands to process.
25	1h	RW/O	Supports Activity LED (SAL) Indicates the SATA controller supports a single output pin (SATALED#) which indicates activity.
24	1h	RW/O	Supports Command List Override (SCLO) When set to 1, indicates that the HBA supports the PxCMD.CLO bit and it's associated function. When cleared to 0, The HBA is not capable of clearing the BSY and DRQ bits in the Status register in order to issue a software reset if these bits are still set from a previous operation.
23:20	3h	RW/O	Interface Speed Support (ISS) Indicates the maximum speed the SATA controller can support on its ports. 1h = 1.5Gb/s 2h = 3Gb/s 3h = 6Gb/s The default of this field is dependent upon the PCH SKU. If at least one PCH SATA port supports 6Gb/s, the default will be 3h. If no PCH SATA ports support 6Gb/s, then the default will be 2h and writes of 3h will be ignored by the PCH. Refer to EDS Vol1 Section 1 for details on 6Gb/s port availability.
19	-	-	Reserved
18	1h	RO	Supports AHCI mode only (SAM) The SATA controller may optionally support AHCI access mechanism only. 0 = SATA controller supports both IDE and AHCI Modes 1 = SATA controller supports AHCI Mode Only Note: BIOS should program this field as “1” since IDE mode is not supported.
17	1h	RW/O	Supports Port Multiplier (SPM) The SATA controller may optionally support command-based switching Port Multipliers. BIOS must clear this bit if Port Multipliers are not supported.
16	-	-	Reserved
15	1h	RO	PIO Multiple DRQ Block (PMD) Hardwired to 1. The SATA controller supports PIO Multiple DRQ Command Block.
14	1h	RW/O	Slumber State Capable (SSC) When set to 1, the SATA controller supports the slumber state.
13	1h	RW/O	Partial State Capable (PSC) When set to 1, the SATA controller supports the partial state.
12:8	1Fh	RO	Number of Command Slots (NCS) Hardwired to 1Fh to indicate support for 32 slots.
7	0h	RO	Command Completion Coalescing Supported (CCCS) 0 = Command Completion Coalescing Not Supported 1 = Command Completion Coalescing Supported
6	0h	RW/O/V	Enclosure Management Supported (EMS) 0 = Enclosure Management Not Supported 1 = Enclosure Management Supported
5	0h	RW/O	Supports External SATA (SXS) 0 = External SATA is not supported on any ports 1 = External SATA is supported on one or more ports When set, software can examine each SATA port’s Command register (PxCMD.ESP) to determine which port is routed externally.
4:0	07h	RO/V	Number of Ports (NP) Indicates number of supported ports. The number of ports indicated in this field may be more than the number of ports indicated in the PI (ABAR + 0Ch) register. Field value dependent on number of ports available in a given SKU.