Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Counter 0 - Interval Timer Status Byte Format Register (C0_ITSBFR) – Offset 40
Each counter's status byte can be read following a Read Back Command. If latch status is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the counter's Counter Access Ports Register (40h for counter 0 and 42h for counter 2) returns the status byte. The status byte returns the following:
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7 | 1b | RO | Counter OUT Pin State (COPS) When this bit is a 1, the OUT pin of the counter is also a 1. |
6 | 1b | RO | Count Register Status (CRSTS) This bit indicates when the last count written to the Count Register (CR) has been loaded into the counting element (CE). The exact time this happens depends on the counter mode, but until the count is loaded into the counting element (CE), the count value will be incorrect. |
5:4 | 00b | RO | Read/Write Selection Status (RW_SLT_STS) These reflect the read/write selection made through bits[5:4] of the control register. The binary codes returned during the status read match the codes used to program the counter read/write selection. |
3:1 | 010b | RO | Mode Selection Status (MD_SLT_STS) These bits return the counter mode programming. The binary code returned matches the code used to program the counter mode, as listed under the bit function above. |
0 | 0b | RO | Countdown Type Status (CDT_STS) This bit reflects the current countdown type, ether 0 for binary countdown or a 1 for binary coded decimal (BCD) countdown. |