Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
General Purpose Event 0 Status [95:64] (GPE0_STS_95_64) – Offset 68
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:0 | 0h | RW/1C/V | General Purpose Event 0 Status [95:64] (GPE0_STS_95_64) These bits are set any time the corresponding GPIO is setup as an input and the corresponding GPIO signal is high (or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPE0_EN_95_64 register, then when the GPE0_STS_95_64 bit is set: |