SSP (GSPI) Time Out (SSTO) – Offset 28 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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SSP (GSPI) Time Out (SSTO) – Offset 28

The Enhanced SSP Time-Out registers have single bit fields that specify the time-out value used to signal a period of inactivity within the Receive FIFO. Note that Writes to reserved bits must be zeroes, and Read value of these bits are undetermined.

Bit Range	Default	Access	Field Name and Description
30:24	-	-	Reserved
23:0	000000h	RW	TIMEOUT (TIMEOUT) Timeout Value Is the value that defines the timeout interval for the rcv FIFO.The Interval is given by TIMEOUT/Parallel (Bus) Clock Frequency. When the number of samples in the Receive FIFO is less than rcv FIFO trigger threshold level, and no additional data is received, the Timeout timer will decrement. The time-out timer is reset after a new sample is received. In DMA Mode of operation this value needs to be set when the Rcv FIFO Trigger Threshold is greater than 1 Rcv FIFO Entry (the required MSize (Single Burst) for SSP DMA peripheral transfers)When in PIO mode of operation this value needs to be set when the total transfer size is not a even divison of the Rcv FIFO trigger threshold level.Is such a case the TIMEOUT value is calculated to be greater than the time to transfer the FIFO Entry size at the desired Bit Rate.

Bit Range

Default

Access

Field Name and Description

30:24

Reserved

23:0

000000h

TIMEOUT (TIMEOUT)

Timeout Value Is the value that defines the timeout interval for the rcv FIFO.The Interval is given by TIMEOUT/Parallel (Bus) Clock Frequency.

When the number of samples in the Receive FIFO is less than rcv FIFO trigger threshold level, and no additional data is received, the Timeout timer will decrement. The time-out timer is reset after a new sample is received.

In DMA Mode of operation this value needs to be set when the Rcv FIFO Trigger Threshold is greater than 1 Rcv FIFO Entry (the required MSize (Single Burst) for SSP DMA peripheral transfers)When in PIO mode of operation this value needs to be set when the total transfer size is not a even divison of the Rcv FIFO trigger threshold level.Is such a case the TIMEOUT value is calculated to be greater than the time to transfer the FIFO Entry size at the desired Bit Rate.

SPI Transmit FIFO (SITF)

SSP (GSPI) Data (SSDR) SPI Transmit FIFO (SITF)