Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
MSI-X Table Base Address Register (MXTBAR) – Offset 344
This register is locked down and cannot be written when GCR.RCL bit is set to '1'.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:1 | 0000000000000000000000000000000b | RW/L | Table Base Address (TBA) This is the value of the Base Address [31:01] assigned by BIOS to allocate separate resources for the memory BAR associated with the MSI-X Table on the PCIe SSD device. |
0 | 0b | RW/L | Table Base Address Valid (TBAV) This bit is set to '1' when BIOS has assigned separate resources for the memory BAR associated with the MSI-X Table on the PCIe SSD device and the Table Base Address (TBA) field is valid. |