Uncorrectable Error Severity (UEV) – Offset 10c - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Uncorrectable Error Severity (UEV) – Offset 10c

This register gives the option to make an uncorrectable error fatal or non-fatal. An error is fatal if the bit is set. An error is non-fatal if the bit is cleared. This register is only reset by a loss of core power.

Bit Range	Default	Access	Field Name and Description
30:22	-	-	Reserved
21	0b	RW/P	ACS Violation Severity (AVS) Severity for ACS violation.
20	0b	RW/P	Unsupported Request Error Severity (URE) Severity for unsupported request reception.
19	0b	RO	ECRC Error Severity (EE) ECRC is not supported.
18	1b	RW/P	Malformed TLP Severity (MT) Severity for malformed TLP reception.
17	1b	RW/P	Receiver Overflow Severity (RO) Severity for receiver overflow occurrences.
16	0b	RW/P	Unexpected Completion Severity (UC) Severity for unexpected completion reception.
15	0b	RW/P	Completor Abort Severity (CA) Severity for completer abort.
14	0b	RW/P	Completion Timeout Severity (CT) Severity for completion timeout.
13	0b	RO	Flow Control Protocol Error Severity (FCPE) Not supported.
12	0b	RW/P	Poisoned TLP Severity (PT) Severity for poisoned TLP reception.
11:6	-	-	Reserved
5	0b	RO	Surprise Down Error Severity (SDE) Surprise Down is not supported.
4	1b	RW/P	Data Link Protocol Error Severity (DLPE) Severity for data link protocol errors.
3:1	-	-	Reserved
0	1b	RO	Training Error Severity (TE) TE not supported. This bit is left as RO=1 for ease of implementation..

Correctable Error Status (CES)

Uncorrectable Error Mask (UEM) Correctable Error Status (CES)