DEVIDLE Control (HECI1_DEVIDLEC) – Offset 800 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Introduction
8254 Timer
Advanced Programmable Interrupt Controller (APIC)
APIC Indirect
CNVi PCI Configuration
DCI PCR
- DCI Control (ECTRL)
EMMC Additional
EMMC Memory Mapped
EMMC PCI Configuration
eMMC PCR
- Dynamic Clock Gating Control (GPPRVRW1)
Enhanced SPI (eSPI) PCI Configuration
eSPI PCR
FIA Configuration PCR
GbE Configuration
GbE Memory Mapped I/O
Generic SPI (GSPI) Additional
Generic SPI (GSPI) DMA Controller
Generic SPI (GSPI) Memory Mapped
GPIO Community 0
GPIO Community 1
GPIO Community 2
GPIO Community 3
GPIO Community 4
GSPI PCI Configuration
High Definition Audio (D31:F3) Memory Mapped I/O
High Definition Audio (D31:F3) PCI Configuration
HPET Memory Mapped
I2C Additional
I2C DMA Controller
I2C Memory Mapped
I2C PCI Congifuration
IDE Redirect PCI Configuration (D22:F2)
Integrated Clock (ICC) Configuration
- CMU_ONE_DWORD25 (cmu_one_dword25)
Intel RST for PCIe Storage (Remapping) PCI Configuration (D24:F0)
Intel RST for PCIe Storage MMIO
Intel(R) Management Engine Interface PCI Configuration
Intel(R) MEI MMIO
- DEVIDLE Control (HECI1_DEVIDLEC)
Intel(R) Trace Hub Configuration
Intel® HD Audio PCR
- Function Configuration (FNCFG)
Interrupt
Interrupt PCR
IO Trap
ISH
ISH PCH Configuration
ISH PCR
- Power Management Control (PMCTL)
Keyboard and Text (KT) Additional Configuration
- Power Management Control and Status (KT_CSXE_PMD_PMCSRBSE_PMCSR)
Keyboard and Text (KT) PCI Configuration (D22:F3)
LPC Configuration
LPC PCR
- General Control And Function Disable (GCFD)
OPI PCR
P2SB PCI Configuration
PCI Express* Port Configuration
PMC I/O Based
PMC Memory Mapped
PMC SSRAM PCI Configuration
Power Management Configuration
Processor Interface Memory
PSF1
PSF2
PSF3
PSF4
PSF5
RTC Indexed
RTC PCR
SATA ABAR
SATA AIDP
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Configuration
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
SATA MXTBA
SDXC (SD Card) PCR
- Dynamic Clock Gating Control (GPPRVRW1)
SDXC Additional Memory Mapped
SDXC Memory Mapped
SDXC PCI Configuration
SMBus Configuration
SMBus I/O and Memory Mapped I/O
SMBus PCR
SMBus TCO I/O
SPI Configuration
SPI Memory Mapped
Thermal Reporting Configuration
Thermal Reporting Memory Mapped
UART Additional Memory Mapped
UART DMA Controller
UART Memory Mapped
UART PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration
xHCI Configuration
xHCI Memory Mapped

DEVIDLE Control (HECI1_DEVIDLEC) – Offset 800

This register allows host to configure the power mode using D0i0/D0i3 support.

Bit Range	Default	Access	Field Name and Description
30:3	-	-	Reserved
2	0b	RW	DevIdle (DEVIDLE) SW sets this bit to 1'b1 to move the function into the DevIdle state. Writing this bit to 1'b0 will return the function to the fully active D0 state (D0i0).
1	0b	RW	Interrupt Request (IR) SW sets this bit to 1'b1 to ask for an interrupt to be generated on completion of the command. SW must clear or set this on each write to this register. When this bit is set to 1'b1, Command-in-Progress deassertion is captured in H_CSR.H_DEVIDLEC_IS. If H_CSR.H_DEVIDLEC_IE is 1b1 as well, host interrupt will be initiated.
0	0b	RO/V	Command-in-Progress (CIP) HW sets this bit on a 1'b1->1'b0 or 1'b0->1'b1 transition of DEVIDLE. While set, the other bits in this register are not valid and it is illegal for SW to write to any bit in this register. HW clears this bit when CSE FW clears its own DevIdle interrupt status bit indicating completion of the DevIdle transition command. When clear, all the other bits in the register are valid and SW may write to any bit. If Interrupt Request (IR) was set for the current command, HW may clear this bit before the interrupt has been made visible to SW, since when SW actually handles a particular interrupt is not visible to the HW. SW writes to this bit have no effect.

Intel(R) Trace Hub Configuration

Intel(R) MEI MMIO Intel(R) Trace Hub Configuration