Normal Interrupt Status (normalintrsts) – Offset 30 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Normal Interrupt Status (normalintrsts) – Offset 30

Bit Range	Default	Access	Field Name and Description
15	0h	RO	Error Interrupt Status (reg_errorintrsts) Error InterruptIf any of the bits in the Register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first. 0 - No Error. 1 – Error
14	0h	RWC1	Boot terminate Interrupt (Boot_Term_Int) This status is set if the boot operation get terminated 0 - Boot operation is not terminated. 1 - Boot operation is terminated
13	0h	RW1C	Boot Acknowlege RCV (FX_event) This status is set if the boot acknowledge is received from device. 0 - Boot ack is not received. 1 - Boot ack is received.
12	0h	RO	Re-Tuning Event (normalintrsts_retuningevent) This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to performre-tuning for next data transfer. Current data transfer (not large block count) can be completed without re-tuning. 1 Re-Tuning should be performed 0 Re-Tuning is not required
11	0h	RO	INT_C (normalintrsts_intc) This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor
10	0h	RO	INT_B (normalintrsts_intb) This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor
9	0h	RO	INT_A (normalintrsts_inta) This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor
8	0h	RO	Card Interrupt (normalintrsts_cardintsts) Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system. when this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again. Interrupt detected by DAT[1] is supported when there is a card per slot. In case of shared bus, interrupt pins are used to detect interrupts. If 000b is set to Interrupt Pin Select in the Shared Bus Control register, this status is effective. Non-zero value is set to Interrupt Pin Select, INT_A, INT_B or INT_C is then used to device interrupts. 0 - No Card Interrupt 1 - Generate Card Interrupt
7	0h	RW/1C	Card Removal (normalintrsts_cardremsts) This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated. 0 - Card State Stable or Debouncing 1 - Card Removed
6	0h	RW/1C	Card Insertion (normalintrsts_cardinssts) This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed.Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated. 0 - Card State Stable or Debouncing 1 - Card Inserted
5	0h	RW/1C	Buffer Read Ready (normalintrsts_bufrdready) This status is set if the Buffer Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure. 0 - Not Ready to read Buffer. 1 - Ready to read Buffer
4	0h	RW/1C	Buffer Write Ready (normalintrsts_bufwrready) This status is set if the Buffer Write Enable changes from 0 to 1. 0 - Not Ready to Write Buffer. 1 - Ready to Write Buffer
3	0h	RW/1C	DMA Interrupt (normalintrsts_dmainterrupt) This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size Register. 0 - No DMA Interrupt 1 - DMA Interrupt is Generated
2	0h	RW/1C	Block Gap Event (normalintrsts_blkgapevent) If the Stop At Block Gap Request in the Block Gap Control Register is set, this bit is set. 0 - No Block Gap Event 1 - Transaction stopped at Block Gap
1	0h	RW/1C	Transfer Complete (normalintrsts_xfercomplete) This bit is set when a read / write transaction is completed. 0 - No Data Transfer Complete 1 - Data Transfer Complete
0	0h	RW/1C	Command Complete (normalintrsts_cmdcomplete) This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23) Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly. 0 - No Command Complete 1 - Command Complete