Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
Port Power Management Status and Control USB2 (PORTPMSCN) – Offset 484
Note that this USB2 Port Power Management Status and Control register is available at the following offsets for all applicable USB2 ports:
USB2 Port 1: 484h
USB2 Port 2: 494h
USB2 Port 3: 4A4h
.....
USB2 Port 9: 504h
USB2 Port 10: 514h
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:28 | 0h | RW/P | Port Test Control (PTC) When this field is ‘0’, the port is not operating in a test mode. (Default) A non-zero value indicates that the port is operating in test mode and the specific test mode is indicated by the specific value. A non-zero Port Test Control value is only valid to a port that is in the Disabled state. If the port is not in this state, the xHC shall respond with the Port Test Control field set to Port Test Control Error. |
27:17 | - | - | Reserved
|
16 | 0b | RW | Hardware LPM Enable (HLE) 0=disable |
15:8 | - | - | Reserved
|
7:4 | 0h | RW/P | Host Initiated Resume Duration (HIRD) Note: This register is sticky. |
3 | 0b | RW/P | Remote Wake Enable (RWE) The host system sets this flag to enable or disable the device for remote wake from L1. |
2:0 | 0h | RW | L1 Status (L1S) Note: This register is sticky. |