Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Extended Test Mode Register 3 (ETR3) – Offset 1048
This register resides in the primary well.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW/V/L | CF9h Lockdown (CF9LOCK) When set, this bit will lock the CF9h Global Reset bit and this register. This register is reset by a CF9h reset. |
30:21 | - | - | Reserved
|
20 | 0b | RW/L | CF9h Global Reset (CF9GR) 1 = a CF9h write of 6h or Eh will cause a Global Reset of both the Host and the ME partitions. |
19:0 | - | - | Reserved
|