xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1) – Offset 8174 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1) – Offset 8174

Bit Range	Default	Access	Field Name and Description
31	0b	RW	Disable scheduler direct transition from IDLE to NO requirement (DIS_SDT_IDL_NR) 0: (default) allow scheduler direct transition from IDLE to NO requirement 1: Disable scheduler direct transition from IDLE to NO requirement
30:26	-	-	Reserved
25	0b	RW	XHCI LTR Transition Policy (XLTRTP) When '0', LTR messaging state machine transitions from High, Medium, or Low LTR states to Active state upon the Alarm Timer timeout and stays in Active until the next service boundary. When '1', the LTR messaging state machine transitions through High-Med-Low to Active states assuming enough latency is available for each transition.
24	0b	RW	XHCI LTR Enable (XLTRE) This bit must be set to enable LTV messaging from XHCI to the PMC.
23:12	400h	RW	Periodic Active LTV (PA_LTV) Bits[23:22] Latency Scale 00b : Reserved 01b : Latency Value to be multiplied by 1024 10b : Latency Value to be multiplied by 32,768 11b : Latency Value to be multiplied by 1,048,576 Bits[21:12] Latency Value (ns). Defaults to 0 micro seconds
11:0	47Dh	RW	USB2 Port L0 LTV (USB2_PL0_LTV) Bits[11:10] Latency Scale 00b : Reserved 01b : Latency Value to be multiplied by 1024 10b : Latency Value to be multiplied by 32,768 11b : Latency Value to be multiplied by 1,048,576 Bits[9:0] Latency Value (ns). Defaults to 128 Micro Seconds

xHC Latency Tolerance Parameters - High Idle Time Control (XLTP_HITC)

xHCI Aux Clock Control Register (XHCI_AUX_CCR) xHC Latency Tolerance Parameters - High Idle Time Control (XLTP_HITC)