Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
I/O Decode Ranges and I/O Enables (ESPI_IOD_IOE) – Offset 80
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
30 | - | - | Reserved
|
29 | 0b | RW | Microcontroller Enable #2 (ME2) Enables decoding of I/O locations 4Eh and 4Fh. |
28 | 0b | RW | SuperI/O Enable (SE) Enables decoding of I/O locations 2Eh and 2Fh. |
27 | 0b | RW | Microcontroller Enable #1 (ME1) Enables decoding of I/O locations 62h and 66h. |
26 | 0b | RW | Keyboard Enable (KE) Enables decoding of the keyboard I/O locations 60h and 64h. |
25 | 0b | RW | High Gameport Enable (HGE) Enables decoding of the I/O locations 208h to 20Fh. |
24 | 0b | RW | Low Gameport Enable (LGE) Enables decoding of the I/O locations 200h to 207h. |
23:20 | - | - | Reserved
|
19 | 0b | RW | Floppy Drive Enable (FDE) Enables decoding of the FDD range. Range is selected by LIOD.FDE |
18 | 0b | RW | Parallel Port Enable (PPE) Enables decoding of the LPT range. Range is selected by LIOD.LPT. |
17 | 0b | RW | Com Port B Enable (CBE) Enables decoding of the COMB range. Range is selected by LIOD.CB. |
16 | 0b | RW | Com Port A Enable (CAE) Enables decoding of the COMA range. Range is selected by LIOD.CA. |
15:13 | - | - | Reserved
|
12 | 0b | RW | FDD Range (FDD) The following table describes which range to decode for the FDD Port |
11:10 | - | - | Reserved
|
9:8 | 00b | RW | LPT Range (LPT) The following table describes which range to decode for the LPT Port: |
7 | - | - | Reserved
|
6:4 | 000b | RW | ComB Range (CB) The following table describes which range to decode for the COMB Port |
3 | - | - | Reserved
|
2:0 | 000b | RW | ComA Range (CA) The following table describes which range to decode for the COMA Port |