Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Error Interrupt Signal Enable (errorintrsigena) – Offset 3a
This register is used to enable the Normal Interrupt Signal register. All the bits are RW, except for Reserved bits, and defined as follows:
0 - Masked
1 - Enabled.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
14:11 | - | - | Reserved
|
10 | 0h | RW | Tuning Error Signal Enable (tune_errsigena)
|
9 | 0h | RW | ADMA Error Signal Enable (adma_errsigena)
|
8 | 0h | RW | Auto CMD Error Signal Enable (autocmd12_errsigena)
|
7 | 0h | RW | Current Limit Error Signal Enable (currentlim_errsigena)
|
6 | 0h | RW | Data End Bit Error Signal Enable (dataendbit_errsigena)
|
5 | 0h | RW | Data CRC Error Signal Enable (datacrc_errsigena)
|
4 | 0h | RW | Data Timeout Error Signal Enable (datatimeout_errsigena)
|
3 | 0h | RW | Command Index Error Signal Enable (cmdindex_errsigena)
|
2 | 0h | RW | Command End Bit Error Signal Enable (cmdendbit_errsigena)
|
1 | 0h | RW | Command CRC Error Signal Enable (cmdcrc_errsigena)
|
0 | 0h | RW | Command Timeout Error Signal Enable (cmdtimeout_errsigena)
|