Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
Control Register High (CTL_HI0) – Offset 81c
NOTE: CTL_HI0 is for DMA Channel 0. The same register definition, CTL_HI1, is available for Channel 1 at address 874h.
CTL_HI0 (CH0): offset 81Ch
CTL_HI1 (CH1): offset 874h
This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled.If status write-back is enabled, CTL_HI is written to then control registers location of the LLI in system memory at the end of the block transfer.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | RW | Channel Class (CH_CLASS) A Class of (N_CHNLS-1) is the highest priority, and 0 is the lowest. This field must be programmed within 0 to (N_CHNLS-1). |
28:18 | - | - | Reserved
|
17 | 0h | RW | DONE (DONE) If status write-back is enabled, the upper word of the control register, |
16:0 | 0h | RW | Block Transfer Size (BLOCK_TS) Block Transfer Size (in Bytes). |