DOI3 Max Power & PG Config (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset a0 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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DOI3 Max Power & PG Config (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset a0

Bit Range	Default	Access	Field Name and Description
30:22	-	-	Reserved
21	1h	RW	Hardware Autonomous Enable (HAE) If set, then the PGCB may request a PGwhenever it is idle.
20	-	-	Reserved
19	1h	RW	Sleep Enable (SLEEP_EN) if clear, then IP will never asset Sleep to the retention flops. Ifset, then IP may assert Sleep during PG'ing.
18	0h	RW	PG Enable (PGE) If clear, then IP will never request a PG. If set, then IP may requestPG when proper conditions are met.
17	0h	RW	I3 Enable (I3_ENABLE) if set, then IP will PG when idle and the D0i3 register (in PGCB) isset. If this bit is set, the IP will not PG unless the IPs D0i3 control bit ='1'. Bit [5] isnot required to be set when this bit is set.
16	1h	RW	PMC Request Enable (PMCRE) When bits [1:0] = ‘11’, power gating is enabled whenever either the D3register or the D0i3 register is set.
15:13	-	-	Reserved
12:10	2h	RW/O	Power On Latency Scale (POW_LAT_SCALE) Support for codes 010 (1us) or 011 (32us) for Exit Latency Scale (1us -) 32mstotal span) only.
9:0	000h	RW/O	Power On Latency value (POW_LAT_VALUE) This value is written by BIOS to communicate to the Driver.

General Purpose Read Write 1 (GEN_REGRW1)

SW LTR update MMIO Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG) General Purpose Read Write 1 (GEN_REGRW1)