Destination Status (DSTAT0) – Offset 828 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

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Destination Status (DSTAT0) – Offset 828

NOTE: DSTAT0 is for DMA Channel 0. The same register definition, DSTAT1, is available for Channel 1 at address 880h.

DSTAT0 (CH0): offset 828h

DSTAT1 (CH1): offset 880h

After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register. This status information is then stored in the DSTATx register and written out to the DSTATx register location of the LLI.

Note : This register is a temporary placeholder for the destination status information on its way to the DSTATx register location of the LLI. The destination status information should be retrieved by software from the DSTATx register location of the LLI and not by a read of this register over the DMA slave interface.

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW	(DSTAT) Destination status information retrieved by hardware from the address pointed to by the contents of the Destination Status Address Register. This register is a temporary placeholder for the destination status information on its way to the DSTATn register location of the LLI. The destination status information should be retrieved by software from the DSTATn register location of the LLI and not by a read of this register over the DMA slave interface.

Bit Range

Default

Access

Field Name and Description

31:0

(DSTAT)

Destination status information retrieved by hardware from the

address pointed to by the contents of the Destination Status Address Register.

This register is a temporary placeholder for the destination status information

on its way to the DSTATn register location of the LLI. The destination status

information should be retrieved by software from the DSTATn register location of

the LLI and not by a read of this register over the DMA slave interface.

DMA Transfer Destination Address High (DAR_HI0)

Source Status (SSTAT0) DMA Transfer Destination Address High (DAR_HI0)