Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0) – Offset 84 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_A_0) – Offset 84

Bit Range	Default	Access	Field Name and Description
30:24	-	-	Reserved
23	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_23) Applied to GPP_A23. Same description as PADCFGLOCKTX_GPP_A_0
22	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_22) Applied to GPP_A22. Same description as PADCFGLOCKTX_GPP_A_0
21	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_21) Applied to GPP_A21. Same description as PADCFGLOCKTX_GPP_A_0
20	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_20) Applied to GPP_A20. Same description as PADCFGLOCKTX_GPP_A_0
19	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_19) Applied to GPP_A19. Same description as PADCFGLOCKTX_GPP_A_0
18	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_18) Applied to GPP_A18. Same description as PADCFGLOCKTX_GPP_A_0
17	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_17) Applied to GPP_A17. Same description as PADCFGLOCKTX_GPP_A_0
16	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_16) Applied to GPP_A16. Same description as PADCFGLOCKTX_GPP_A_0
15	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_15) Applied to GPP_A15. Same description as PADCFGLOCKTX_GPP_A_0
14	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_14) Applied to GPP_A14. Same description as PADCFGLOCKTX_GPP_A_0
13	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_13) Applied to GPP_A13. Same description as PADCFGLOCKTX_GPP_A_0
12	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_12) Applied to GPP_A12. Same description as PADCFGLOCKTX_GPP_A_0
11	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_11) Applied to GPP_A11. Same description as PADCFGLOCKTX_GPP_A_0
10	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_10) Applied to GPP_A10. Same description as PADCFGLOCKTX_GPP_A_0
9	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_9) Applied to GPP_A9. Same description as PADCFGLOCKTX_GPP_A_0
8	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_8) Applied to GPP_A8. Same description as PADCFGLOCKTX_GPP_A_0
7	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_7) Applied to GPP_A7. Same description as PADCFGLOCKTX_GPP_A_0
6	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_6) Applied to GPP_A6. Same description as PADCFGLOCKTX_GPP_A_0
5	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_5) Applied to GPP_A5. Same description as PADCFGLOCKTX_GPP_A_0
4	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_4) Applied to GPP_A4. Same description as PADCFGLOCKTX_GPP_A_0.
3	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_3) Applied to GPP_A3. Same description as PADCFGLOCKTX_GPP_A_0.
2	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_2) Applied to GPP_A2. Same description as PADCFGLOCKTX_GPP_A_0.
1	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_1) Applied to GPP_A1. Same description as PADCFGLOCKTX_GPP_A_0
0	0b	RW	Pad Config Lock TXState (PADCFGLOCKTX_GPPC_A_0) PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read-Only and software writes to the register have no effect. 0 = Unlock 1 = Locks the Pad Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.