Extended General Configuration Register (EGCR) – Offset 354 - 1.2 - ID:615146 | Intel® 400 Series Chipset On-Package Platform Controller Hub

Intel® 400 Series Chipset On-Package Platform Controller Hub

Online Register Database

ID	Date	Version	Classification
615146	08/09/2019	1.2	Public

Extended General Configuration Register (EGCR) – Offset 354

Bit Range	Default	Access	Field Name and Description
30:21	-	-	Reserved
20	0b	RW	To SATA CLKREQ Assertion Select (TSCAS) When this bit is set to '1', internal CLKREQ assertion to SATA is triggered when cycle has been committed to SATA. When this bit is '0', internal CLKREQ assertion to SATA is triggered based on ISM in non-IDLE states.
19:18	-	-	Reserved
17	0b	RW	Cycle Rouster Trunk Clock Gating Enable (CRTCGE) When this bit is set to '1', trunk clock gating is enabled in Cycle Router. When this bit is '0' (reset default), trunk clock gating is disabled in Cycle Router.
16	0b	RW	Cycle Router Dynamic Clock Gating Enable (CRDCGE) When this bit is set to '1', dynamic local clock gating is enabled in Cycle Router. When this bit is '0' (reset default), dynamic local clock gating is disabled in Cycle Router.
15	0b	RW	Single Remapping Mode (SRM) When this bit is set to '1', for a downstream non-posted cycle that remap to multiple Cycle Routers or PCIe devices, the remapped non-posted requests to each of the Cycle Routers or PCIe devices are initiated one at a time, with subsequent request initiated only after the prior completion is received. When this bit is '0', the remapped non-posted requests to each of the Cycle Routers or PCIe devices are initiated back-to-back resulting in multiple non-posted pending without waiting for the completion of the prior cycle.
14:12	-	-	Reserved
11	0b	RW	Downstream Configuration Flush Enable (DCFE) When set to '1', all downstream configuration cycles to AHCI controller unrelated to PCIe device will still be forwarded by HW to the PCIe device with all byte enables inactive to achieve the flushing effect. When this bit is '0', all downstream configuration cycles to AHCI controller unrelated to PCIe device will not be forwarded by HW.
10	0b	RW	Downstream I/O Flush Enable (DIOFE) When set to '1', all downstream I/O cycles to AHCI controller outside the remapped range of PCIe device will still be forwarded by HW to the PCIe device with all byte enables inactive to achieve the flushing effect. When this bit is '0', all downstream I/O cycles to AHCI controller outside the remapped range of PCIe device will not be forwarded by HW.
9	0b	RW	Downstream Memory Read Flush Enable (DMRFE) When set to '1', all downstream memory reads to AHCI controller outside the remapped range of PCIe device will still be forwarded by HW to the PCIe device with all byte enables inactive to achieve the flushing effect. When this bit is '0', all downstream memory reads to AHCI controller outside the remapped range of PCIe device will not be forwarded by HW.
8	0b	RW	MSI 64-bit Message Address Support (MSI64E) When set, NAND Cycle Router shall enable the 64-bit message address support for MSI. When clear (default), NAND Cycle Router shall enable the 32-bit message address support for MSI.
7:0	-	-	Reserved