Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
SSP (GSPI) Control Register 0 (SSCR0) – Offset 0
All bits must be set to the preferred value before enabling the Enhanced SSP. Note that Writes to reserved bits must be zeroes, and Read values of these bits is undetermined.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RW | MOD (MOD) ModeSet to 0 - Normal SSP Mode : Full Duplex Serial peripheral interface. |
30 | 0b | RW | ACS (ACS) Audio Clock Select |
29:24 | - | - | Reserved
|
23 | 0b | RW | TIM (TIM) Transmit FIFO Under Run Interrupt Mask |
22 | 0b | RW | RIM (RIM) Receive FIFO Over Run Interrupt Mask |
21 | 0b | RW | NCS (NCS) Network Clock SelectThe SSCR0.NCS bit in conjunction with SSCR0.ECS determines which clock is used. |
20 | 0b | RW | EDSS (EDSS) Extended Data Size SelectThe 1-bit extended field is used in conjunction with the data size select SSCR0.DSS bits to select the size of the data transmitted and received by the Enhanced SSP. |
19:8 | 0h | RW | SCR (SCR) Serial Clock Rate |
7 | 0b | RW | SSE (SSE) Synchronous Serial Port Enable |
6 | 0b | RW | ECS (ECS) External Clock Select:0 = use On-chip clock (output of M/N Divider) to produce the SSP's serial clock (SSPSCLK). Selects the use of the the output of the M/N Divider (MBAR0 + 0x800, CLOCKS) to create the SSP's serial clock (SSPCLK) |
5:4 | 00b | RW | FRF (FRF) Frame FormatSet to 00 - Motorola Serial Peripheral Interface (SPI) |
3:0 | 0000b | RW | DSS (DSS) Data Size Select |