Intel® 400 Series Chipset On-Package Platform Controller Hub
Online Register Database
ID | Date | Version | Classification |
---|---|---|---|
615146 | 08/09/2019 | 1.2 | Public |
Capabilities (capabilities) – Offset 40
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
63 | 0h | RO | HS 400 Support (HS_400) This field indicates whether HS400 is supported or not. |
62:56 | - | - | Reserved
|
55:48 | 00h | RO | Clock Multiplier (clk_mult) This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register.Setting 00h means that Host Controller does not support programmable clock generator.FFh: Clock Multiplier M = 256.... |
47:46 | 0h | RO | Re-tuning modes (re_tuning_modes) This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver |
45 | 0h | RO | Use Tuning for SDR50 (use_tung_sdr50) If this bit is set to 1, this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.) |
44 | - | - | Reserved
|
43:40 | 0h | RO | Timer Count for Re-Tuning (timer_cnt_retung) This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. |
39 | - | - | Reserved
|
38 | 0h | RO | Driver Type D Support (drv_typeD_support) This bit indicates support of Driver Type D for 1.8 Signaling. |
37 | 0h | RO | Driver Type C Support (drvtypeC_support) This bit indicates support of Driver Type C for 1.8 Signaling. |
36 | 0h | RO | Driver Type A Support (drvtypeA_support) This bit indicates support of Driver Type A for 1.8 Signaling. |
35 | - | - | Reserved
|
34 | 1h | RO | DDR50 Support (ddr50_support) This bit indicates whether DDR50 is supported. |
33 | 1h | RO | SDR104 Support (sdr104support) This bit indicates whether SDR104 is supported. |
32 | 1h | RO | SDR50 Support (sdr50_support) This bit indicates whether SDR50 is supported. |
31:30 | 0h | RO | Slot Type (slot_type) This field indicates usage of a slot by a specific Host System. (A host controller register set is defined per slot.) Embedded slot for one device (01b) means that only one on-removable device is connected to a SD bus slot. Shared Bus Slot (10b) can be set if Host Controller supports Shared Bus Control register. |
29 | 1h | RO | Asynchronous Interrupt Support (asynch_intr_support) This bit indicates whether the HC supports Asynchronous Interrupt. |
28 | 1h | RO | 64-bit System Bus Support (sys_addr_64bit_support_v3) This bit indicates whether the HC supports 64bit System Bus |
27 | - | - | Reserved
|
26 | 1h | RO | Voltage Support 1.8V (volt1p8_support) This bit indicates whether the HC supports 1.8V. |
25 | 0h | RO | Voltage Support 3.0V (volt3p0_support) This bit indicates whether the HC supports 3.0V. |
24 | 1h | RO | Voltage Support 3.3V (volt3p3_support) This bit indicates whether the HC supports 3.3V. |
23 | 0h | RO | Suspend / Resume Support (susp_resume_support) This bit indicates whether the HC supports Suspend/Resume functionality. |
22 | 0h | RO | SDMA Support (sdma_support) This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. (SDMA Mode) |
21 | 1h | RO | High Speed Support (high_speed_support) This bit indicates whether the HC and the Host System support High Speed mode. |
20 | - | - | Reserved
|
19 | 1h | RO | ADMA2 Support (adma2_support) ADMA2 Not Supported. Hardwired to 1. |
18 | 0h | RO | 8 bit support for embedded device (extd_media_bus) This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. |
17:16 | 0h | RO | Max Block Length (max_blk_length) This value indicates the maximum block size that the HD can read and write to the buffer in the HC. |
15:8 | C8h | RO | Base Clock Frequency for SD Clock (base_clk_freq) 1) 6-bit Base Clock Frequency |
7 | 1h | RO | Timeout Clock Unit (timeout_clk_unit) This bit shows the unit of base clock frequency used to detect Data Timeout Error. |
6 | - | - | Reserved
|
5:0 | 01h | RO | Timeout Clock Frequency (timeout_clkf_req) This bit shows the base clock frequency used to detect Data Timeout Error.Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz000000b - Get Information via another method. |